1. Field of the Invention
This invention relates generally to a digital coding apparatus and to a digital coding/decoding apparatus. More specifically the present invention pertains to a technique of reducing the size of logical tables for use by these apparatus.
2. Art Background
Japanese Patent Application, published under Pub. No. 6-165112, shows a digital coding/decoding apparatus for image data compression and expansion. FIG. 10 shows a conventional digital coding/decoding apparatus. 14 is a discrete cosine transform circuit (DCT). 15 is a quantizer. 16 is a variable-length coder (VLC). 17 is an inverse discrete cosine transform circuit (IDCT). 18 is an inverse quantizer. 19 is a variable-length decoder (VLD). 20 is a circuit made up of the VLC 16 and the VLD 19.
The DCT 14 receives either an image data luminance signal or an image data chrominance signal and performs a discrete cosine transform on the received signal, a result of the discrete cosine transform operation being put out in the form of an AC coefficient. The quantizer 15 quantizes an output of the DCT 14, a result of the quantization operation being put out. The VLC 16 transforms an output of the quantizer 15 into a variable-length Huffman code for further data compression. This variable-length AC code is padded to a fixed-length code. This fixed-length code is put out to a recording device (not shown) located outside the apparatus.
The VLD 19 receives a fixed-length AC code (i.e., a Huffman code) from a recording device (not shown in the figure) located outside the apparatus, extracts a variable-length AC code from the received fixed-length AC code, and decodes and expands the variable-length Huffman code to put out an AC coefficient. The inverse quantizer 18 inverse-quantizes an output of the VLD 19, a result of the inverse-quantization operation being put out. The IDCT 17 performs an inverse discrete cosine transform on an output of the inverse quantizer 18, to obtain either an image data luminance signal or an image data chrominance signal. Such an obtained signal is fed to an image display unit (e.g., a CRT) located outside the apparatus.
FIG. 7 schematically shows a circuit organization of the VLC 16 of FIG. 10. 1 is a decision circuit. 2 is a run length counter. 3 is an AC code table. 4 is a two-dimensional Huffman coding circuit. 7 is a padding circuit. 12 is a code length calculation circuit. 13 is an AC code length table.
As shown in FIG. 11, the decision circuit 1 receives a sequence of AC coefficients each of which has either a value of zero (zero value) or a value other than zero (nonzero value). Upon receipt of an AC coefficient the decision circuit 1 determines whether the AC coefficient received has a zero value or a nonzero value. The run length counter 2 counts the number of times the decision circuit 1 successively receives a zero-valued AC coefficient (i.e., the number of consecutive AC coefficients that are all determined by the run length counter 2 having a zero value). Whereas a nonzero-valued AC coefficient is defined as VALUE, the number of consecutive zero-valued AC coefficients is defined as ZERO RUN (ZERORUN). ZERORUN and VALUE combinations are shown in FIG. 11. The AC code table 3 prestores ZERORUN-VALUE combinations and variable-length AC codes in corresponding relationship. Additionally the AC code length table 13 prestores the ZERORUN-VALUE combinations and code lengths of the variable-length AC codes in corresponding relationship. Each ZERORUN-VALUE combination is fed to the two-dimensional Huffman coding circuit 4 and to the code length calculation circuit 12. Based on the AC code table 3, the Huffman coding circuit 4 puts out a variable-length AC code corresponding to the ZERORUN-VALUE combination received. Based on the AC code length table 13, the code length calculation circuit 12 puts out a code length of a variable-length AC code corresponding to the ZERORUN-VALUE combination received. The padding circuit 7 receives the variable-length AC code from the two-dimensional Huffman coding circuit 4 and the code length from the code length calculation circuit 12. Then the padding circuit 7 pads these data items, received from the Huffman coding circuit 4 and the calculation circuit 12, to a fixed-length AC code (see FIG. 12). FIG. 12 depicts an example of padding thirteen variable-length AC codes A to M into three fixed-length codes. A part of the variable-length AC code E, i.e., El, is padded to the first of the three fixed-length codes, and the remaining part of the variable-length AC code E, i.e., E2, is padded to the head end of the second of the three fixed-length codes.
FIG. 8 illustrates a circuit organization of the VLD 19. 5 is a code length calculation circuit. 6 is an AC code length table. 9 is a two-dimensional Huffman decoding circuit. 10 is an extraction circuit. 11 is an inverse AC code table.
When the VLD 19 receives a fixed-length code, the code length calculation circuit 5 finds from the fixed-length AC code a code length of a variable-length AC code contained in the fixed-length AC code, according to the AC code length table 6. The extraction circuit 10 receives a fixed-length AC code and the code length found by the code length calculation circuit 5 and extracts a variable-length AC code from the fixed-length code. Based on the inverse AC code table 11, the two-dimensional Huffman decoding circuit 9 transforms the extracted variable-length AC code into a ZERORUN-VALUE combination.
FIG. 9 is a list of different types of logical tables for use by the VLC 16 and the VLD 19 of FIG. 10, namely a variable-length-code encode table T1, a code length table T2, a code length table T3, and a variable-length-code decode table T4. TABLE T1, which corresponds to the AC code table 3, takes in a ZERORUN-VALUE combination and puts out a variable-length code. TABLE T2, which corresponds to the AC code length table 13, takes in a ZERORUN-VALUE combination and puts out a code length. TABLE T3, which corresponds to the AC code length table 6, takes in a variable-length code and puts out a code length thereof. TABLE T4, which corresponds to the inverse AC code table 11, takes in a variable-length code and puts out a ZERORUN-VALUE combination.
The above-described conventional coding/decoding apparatus, however, presents some problems. For the case of a code length table (maximum ZERORUN: 63; maximum VALUE: 255; maximum code length: 16), such a code length table, when formed by RAMs or ROMs, requires a structure of 64.times.256=16384 words including AC codes without ZERORUN and AC codes without VALUE. If one word is made up of five bits on the average, then a total of 16384.times.5=81920 bits is required. This increases the table size, resulting in increasing the size of peripheral circuits of a code length table. Much more power is dissipated.
There is a conventional way of reducing the size of logical tables which can be expressed as follows: EQU (z, v)=(z-1, 0)+(0, v)
where z=ZERORUN and v=VALUE. For example, as shown in FIG. 13, if z=10 and v=2, then division is made as follows. EQU (10, 2)=(9, 0)+(0, 2)
This method can provide a logical table of 62+255=317 words. 317 words is still large for the size of logical tables.